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uint32_t condition_id, src1_id, src2_id, type_id, val_id;
unsigned int component_count;
assert(dst[0].write_mask == dst[1].write_mask);
condition_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], dst->write_mask);
src1_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[1], dst->write_mask);
src2_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[2], dst->write_mask);
component_count = vkd3d_write_mask_component_count(dst->write_mask);
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_FLOAT, component_count);
condition_id = vkd3d_dxbc_compiler_emit_int_to_bool(compiler,
VKD3D_SHADER_CONDITIONAL_OP_NZ, component_count, condition_id);
val_id = vkd3d_spirv_build_op_select(builder, type_id, condition_id, src2_id, src1_id);
vkd3d_dxbc_compiler_emit_store_dst(compiler, &dst[0], val_id);
val_id = vkd3d_spirv_build_op_select(builder, type_id, condition_id, src1_id, src2_id);
vkd3d_dxbc_compiler_emit_store_dst(compiler, &dst[1], val_id);
}
static void vkd3d_dxbc_compiler_emit_dot(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t type_id, val_id, src_ids[2];
DWORD write_mask;
unsigned int i;
assert(vkd3d_write_mask_component_count(dst->write_mask) == 1);
if (instruction->handler_idx == VKD3DSIH_DP4)
write_mask = VKD3DSP_WRITEMASK_ALL;
else if (instruction->handler_idx == VKD3DSIH_DP3)
write_mask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1 | VKD3DSP_WRITEMASK_2;
else
write_mask = VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1;
assert(instruction->src_count == ARRAY_SIZE(src_ids));
for (i = 0; i < ARRAY_SIZE(src_ids); ++i)
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src_ids[i] = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[i], write_mask);
type_id = vkd3d_spirv_get_type_id(builder,
vkd3d_component_type_from_data_type(dst->reg.data_type), 1);
val_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream,
SpvOpDot, type_id, src_ids[0], src_ids[1]);
vkd3d_dxbc_compiler_emit_store_dst(compiler, dst, val_id);
static void vkd3d_dxbc_compiler_emit_rcp(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t type_id, src_id, val_id;
unsigned int component_count;
component_count = vkd3d_write_mask_component_count(dst->write_mask);
type_id = vkd3d_spirv_get_type_id(builder,
vkd3d_component_type_from_data_type(dst->reg.data_type), component_count);
src_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src, dst->write_mask);
val_id = vkd3d_spirv_build_op_fdiv(builder, type_id,
vkd3d_dxbc_compiler_get_constant_float_vector(compiler, 1.0f, component_count), src_id);
vkd3d_dxbc_compiler_emit_store_dst(compiler, dst, val_id);
}
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static void vkd3d_dxbc_compiler_emit_imul(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t type_id, val_id, src0_id, src1_id;
unsigned int component_count;
if (dst[0].reg.type != VKD3DSPR_NULL)
FIXME("Extended multiplies not implemented.\n"); /* SpvOpSMulExtended */
if (dst[1].reg.type == VKD3DSPR_NULL)
return;
component_count = vkd3d_write_mask_component_count(dst[1].write_mask);
type_id = vkd3d_spirv_get_type_id(builder,
vkd3d_component_type_from_data_type(dst[1].reg.data_type), component_count);
src0_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], dst[1].write_mask);
src1_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[1], dst[1].write_mask);
val_id = vkd3d_spirv_build_op_imul(builder, type_id, src0_id, src1_id);
vkd3d_dxbc_compiler_emit_store_dst(compiler, &dst[1], val_id);
}
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static void vkd3d_dxbc_compiler_emit_imad(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t type_id, val_id, src_ids[3];
unsigned int i, component_count;
component_count = vkd3d_write_mask_component_count(dst->write_mask);
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_INT, component_count);
for (i = 0; i < ARRAY_SIZE(src_ids); ++i)
src_ids[i] = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[i], dst->write_mask);
val_id = vkd3d_spirv_build_op_imul(builder, type_id, src_ids[0], src_ids[1]);
val_id = vkd3d_spirv_build_op_iadd(builder, type_id, val_id, src_ids[2]);
vkd3d_dxbc_compiler_emit_store_dst(compiler, dst, val_id);
}
static void vkd3d_dxbc_compiler_emit_udiv(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
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uint32_t type_id, val_id, src0_id, src1_id, condition_id, uint_max_id;
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
unsigned int component_count = 0;
if (dst[0].reg.type != VKD3DSPR_NULL)
{
component_count = vkd3d_write_mask_component_count(dst[0].write_mask);
type_id = vkd3d_spirv_get_type_id(builder,
vkd3d_component_type_from_data_type(dst[0].reg.data_type), component_count);
src0_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], dst[0].write_mask);
src1_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[1], dst[0].write_mask);
condition_id = vkd3d_dxbc_compiler_emit_int_to_bool(compiler,
VKD3D_SHADER_CONDITIONAL_OP_NZ, component_count, src1_id);
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uint_max_id = vkd3d_dxbc_compiler_get_constant_uint_vector(compiler,
0xffffffff, component_count);
val_id = vkd3d_spirv_build_op_udiv(builder, type_id, src0_id, src1_id);
/* The SPIR-V spec says: "The resulting value is undefined if Operand 2 is 0." */
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val_id = vkd3d_spirv_build_op_select(builder, type_id, condition_id, val_id, uint_max_id);
vkd3d_dxbc_compiler_emit_store_dst(compiler, &dst[0], val_id);
}
if (dst[1].reg.type != VKD3DSPR_NULL)
{
if (!component_count || dst[0].write_mask != dst[1].write_mask)
{
component_count = vkd3d_write_mask_component_count(dst[1].write_mask);
type_id = vkd3d_spirv_get_type_id(builder,
vkd3d_component_type_from_data_type(dst[1].reg.data_type), component_count);
src0_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], dst[1].write_mask);
src1_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[1], dst[1].write_mask);
condition_id = vkd3d_dxbc_compiler_emit_int_to_bool(compiler,
VKD3D_SHADER_CONDITIONAL_OP_NZ, component_count, src1_id);
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uint_max_id = vkd3d_dxbc_compiler_get_constant_uint_vector(compiler,
0xffffffff, component_count);
}
val_id = vkd3d_spirv_build_op_umod(builder, type_id, src0_id, src1_id);
/* The SPIR-V spec says: "The resulting value is undefined if Operand 2 is 0." */
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val_id = vkd3d_spirv_build_op_select(builder, type_id, condition_id, val_id, uint_max_id);
vkd3d_dxbc_compiler_emit_store_dst(compiler, &dst[1], val_id);
}
}
static void vkd3d_dxbc_compiler_emit_bitfield_instruction(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t src_ids[4], result_id, type_id, mask_id;
unsigned int i, j, src_count;
DWORD write_mask;
SpvOp op;
src_count = instruction->src_count;
assert(2 <= src_count && src_count <= ARRAY_SIZE(src_ids));
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_UINT, 1);
mask_id = vkd3d_dxbc_compiler_get_constant_uint(compiler, 0x1f);
switch (instruction->handler_idx)
{
case VKD3DSIH_BFI: op = SpvOpBitFieldInsert; break;
case VKD3DSIH_IBFE: op = SpvOpBitFieldSExtract; break;
case VKD3DSIH_UBFE: op = SpvOpBitFieldUExtract; break;
default:
ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
return;
}
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
{
if (!(write_mask = dst->write_mask & (VKD3DSP_WRITEMASK_0 << i)))
continue;
for (j = 0; j < src_count; ++j)
src_ids[src_count - j - 1] = vkd3d_dxbc_compiler_emit_load_reg(compiler,
&src[j].reg, src[j].swizzle, write_mask);
for (j = src_count - 2; j < src_count; ++j)
{
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uint32_t int_type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_INT, 1);
src_ids[j] = vkd3d_spirv_build_op_and(builder, int_type_id, src_ids[j], mask_id);
}
result_id = vkd3d_spirv_build_op_trv(builder, &builder->function_stream,
op, type_id, src_ids, src_count);
vkd3d_dxbc_compiler_emit_store_reg(compiler, &dst->reg, write_mask, result_id);
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static void vkd3d_dxbc_compiler_emit_f16tof32(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
uint32_t instr_set_id, type_id, scalar_type_id, src_id, result_id;
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
DWORD write_mask;
unsigned int i;
instr_set_id = vkd3d_spirv_get_glsl_std450_instr_set(builder);
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_FLOAT, 2);
scalar_type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_FLOAT, 1);
/* FIXME: Consider a single UnpackHalf2x16 intruction per 2 components. */
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
{
if (!(write_mask = dst->write_mask & (VKD3DSP_WRITEMASK_0 << i)))
continue;
src_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src, write_mask);
result_id = vkd3d_spirv_build_op_ext_inst(builder, type_id,
instr_set_id, GLSLstd450UnpackHalf2x16, &src_id, 1);
result_id = vkd3d_spirv_build_op_composite_extract1(builder,
scalar_type_id, result_id, 0);
vkd3d_dxbc_compiler_emit_store_reg(compiler, &dst->reg, write_mask, result_id);
}
}
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static void vkd3d_dxbc_compiler_emit_f32tof16(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
uint32_t instr_set_id, type_id, scalar_type_id, src_id, zero_id, constituents[2], result_id;
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
DWORD write_mask;
unsigned int i;
instr_set_id = vkd3d_spirv_get_glsl_std450_instr_set(builder);
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_FLOAT, 2);
scalar_type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_UINT, 1);
zero_id = vkd3d_dxbc_compiler_get_constant_float(compiler, 0.0f);
/* FIXME: Consider a single PackHalf2x16 intruction per 2 components. */
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
{
if (!(write_mask = dst->write_mask & (VKD3DSP_WRITEMASK_0 << i)))
continue;
src_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src, write_mask);
constituents[0] = src_id;
constituents[1] = zero_id;
src_id = vkd3d_spirv_build_op_composite_construct(builder,
type_id, constituents, ARRAY_SIZE(constituents));
result_id = vkd3d_spirv_build_op_ext_inst(builder, scalar_type_id,
instr_set_id, GLSLstd450PackHalf2x16, &src_id, 1);
vkd3d_dxbc_compiler_emit_store_reg(compiler, &dst->reg, write_mask, result_id);
}
}
static void vkd3d_dxbc_compiler_emit_comparison_instruction(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t src0_id, src1_id, type_id, result_id;
unsigned int component_count;
SpvOp op;
switch (instruction->handler_idx)
{
case VKD3DSIH_EQ: op = SpvOpFOrdEqual; break;
case VKD3DSIH_GE: op = SpvOpFOrdGreaterThanEqual; break;
case VKD3DSIH_IEQ: op = SpvOpIEqual; break;
case VKD3DSIH_IGE: op = SpvOpSGreaterThanEqual; break;
case VKD3DSIH_ILT: op = SpvOpSLessThan; break;
case VKD3DSIH_INE: op = SpvOpINotEqual; break;
case VKD3DSIH_LT: op = SpvOpFOrdLessThan; break;
case VKD3DSIH_NE: op = SpvOpFUnordNotEqual; break;
case VKD3DSIH_UGE: op = SpvOpUGreaterThanEqual; break;
case VKD3DSIH_ULT: op = SpvOpULessThan; break;
default:
ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
return;
}
component_count = vkd3d_write_mask_component_count(dst->write_mask);
src0_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], dst->write_mask);
src1_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[1], dst->write_mask);
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_BOOL, component_count);
result_id = vkd3d_spirv_build_op_tr2(builder, &builder->function_stream,
op, type_id, src0_id, src1_id);
result_id = vkd3d_dxbc_compiler_emit_bool_to_int(compiler, component_count, result_id);
vkd3d_dxbc_compiler_emit_store_reg(compiler, &dst->reg, dst->write_mask, result_id);
}
static void vkd3d_dxbc_compiler_emit_breakc(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction, uint32_t target_block_id)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t condition_id, merge_block_id;
condition_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src, VKD3DSP_WRITEMASK_0);
condition_id = vkd3d_dxbc_compiler_emit_int_to_bool(compiler, instruction->flags, 1, condition_id);
merge_block_id = vkd3d_spirv_alloc_id(builder);
vkd3d_spirv_build_op_selection_merge(builder, merge_block_id, SpvSelectionControlMaskNone);
vkd3d_spirv_build_op_branch_conditional(builder, condition_id, target_block_id, merge_block_id);
vkd3d_spirv_build_op_label(builder, merge_block_id);
}
static void vkd3d_dxbc_compiler_emit_output_setup_invocation(struct vkd3d_dxbc_compiler *compiler)
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struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
uint32_t void_id, function_id, arguments[MAX_REG_OUTPUT];
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if ((function_id = compiler->output_setup_function_id))
{
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void_id = vkd3d_spirv_get_op_type_void(builder);
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for (i = 0, count = 0; i < ARRAY_SIZE(compiler->private_output_variable); ++i)
{
if (compiler->private_output_variable[i])
arguments[count++] = compiler->private_output_variable[i];
}
vkd3d_spirv_build_op_function_call(builder, void_id, function_id, arguments, count);
}
}
static void vkd3d_dxbc_compiler_emit_return(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
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vkd3d_dxbc_compiler_emit_output_setup_invocation(compiler);
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vkd3d_spirv_build_op_return(builder);
static void vkd3d_dxbc_compiler_emit_kill(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t condition_id, target_block_id, merge_block_id;
condition_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src, VKD3DSP_WRITEMASK_0);
condition_id = vkd3d_dxbc_compiler_emit_int_to_bool(compiler, instruction->flags, 1, condition_id);
merge_block_id = vkd3d_spirv_alloc_id(builder);
target_block_id = vkd3d_spirv_alloc_id(builder);
vkd3d_spirv_build_op_selection_merge(builder, merge_block_id, SpvSelectionControlMaskNone);
vkd3d_spirv_build_op_branch_conditional(builder, condition_id, target_block_id, merge_block_id);
vkd3d_spirv_build_op_label(builder, target_block_id);
vkd3d_spirv_build_op_kill(builder);
vkd3d_spirv_build_op_label(builder, merge_block_id);
}
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static struct vkd3d_control_flow_info *vkd3d_dxbc_compiler_push_control_flow_level(
struct vkd3d_dxbc_compiler *compiler)
{
if (!vkd3d_array_reserve((void **)&compiler->control_flow_info, &compiler->control_flow_info_size,
compiler->control_flow_depth + 1, sizeof(*compiler->control_flow_info)))
{
ERR("Failed to allocate control flow info structure.\n");
return NULL;
}
return &compiler->control_flow_info[compiler->control_flow_depth++];
}
static void vkd3d_dxbc_compiler_pop_control_flow_level(struct vkd3d_dxbc_compiler *compiler)
{
struct vkd3d_control_flow_info *cf_info;
assert(compiler->control_flow_depth);
cf_info = &compiler->control_flow_info[--compiler->control_flow_depth];
memset(cf_info, 0, sizeof(*cf_info));
}
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static struct vkd3d_control_flow_info *vkd3d_dxbc_compiler_find_innermost_breakable_cf_construct(
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struct vkd3d_dxbc_compiler *compiler)
{
int depth;
for (depth = compiler->control_flow_depth - 1; depth >= 0; --depth)
{
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if (compiler->control_flow_info[depth].current_block == VKD3D_BLOCK_LOOP
|| compiler->control_flow_info[depth].current_block == VKD3D_BLOCK_SWITCH)
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return &compiler->control_flow_info[depth];
}
return NULL;
}
static void vkd3d_dxbc_compiler_emit_control_flow_instruction(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
uint32_t loop_header_block_id, loop_body_block_id, continue_block_id;
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t merge_block_id, val_id, condition_id, true_label;
struct vkd3d_control_flow_info *cf_info;
cf_info = compiler->control_flow_depth
? &compiler->control_flow_info[compiler->control_flow_depth - 1] : NULL;
switch (instruction->handler_idx)
{
case VKD3DSIH_IF:
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if (!(cf_info = vkd3d_dxbc_compiler_push_control_flow_level(compiler)))
val_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src, VKD3DSP_WRITEMASK_0);
condition_id = vkd3d_dxbc_compiler_emit_int_to_bool(compiler, instruction->flags, 1, val_id);
true_label = vkd3d_spirv_alloc_id(builder);
merge_block_id = vkd3d_spirv_alloc_id(builder);
vkd3d_spirv_build_op_selection_merge(builder, merge_block_id, SpvSelectionControlMaskNone);
cf_info->u.if_.stream_location = vkd3d_spirv_stream_current_location(&builder->function_stream);
vkd3d_spirv_build_op_branch_conditional(builder, condition_id, true_label, merge_block_id);
vkd3d_spirv_build_op_label(builder, true_label);
cf_info->u.if_.id = compiler->branch_id;
cf_info->u.if_.merge_block_id = merge_block_id;
cf_info->u.if_.else_block_id = 0;
cf_info->inside_block = true;
cf_info->current_block = VKD3D_BLOCK_IF;
vkd3d_spirv_build_op_name(builder, merge_block_id, "branch%u_merge", compiler->branch_id);
vkd3d_spirv_build_op_name(builder, true_label, "branch%u_true", compiler->branch_id);
++compiler->branch_id;
break;
case VKD3DSIH_ELSE:
assert(compiler->control_flow_depth);
assert(cf_info->current_block == VKD3D_BLOCK_IF);
if (cf_info->inside_block)
vkd3d_spirv_build_op_branch(builder, cf_info->u.if_.merge_block_id);
cf_info->u.if_.else_block_id = vkd3d_spirv_alloc_id(builder);
vkd3d_spirv_as_op_branch_conditional(&builder->function_stream,
cf_info->u.if_.stream_location)->false_label = cf_info->u.if_.else_block_id;
vkd3d_spirv_build_op_name(builder,
cf_info->u.if_.else_block_id, "branch%u_false", cf_info->u.if_.id);
vkd3d_spirv_build_op_label(builder, cf_info->u.if_.else_block_id);
cf_info->inside_block = true;
break;
case VKD3DSIH_ENDIF:
assert(compiler->control_flow_depth);
assert(cf_info->current_block == VKD3D_BLOCK_IF);
if (cf_info->inside_block)
vkd3d_spirv_build_op_branch(builder, cf_info->u.if_.merge_block_id);
vkd3d_spirv_build_op_label(builder, cf_info->u.if_.merge_block_id);
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vkd3d_dxbc_compiler_pop_control_flow_level(compiler);
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if (!(cf_info = vkd3d_dxbc_compiler_push_control_flow_level(compiler)))
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return;
loop_header_block_id = vkd3d_spirv_alloc_id(builder);
loop_body_block_id = vkd3d_spirv_alloc_id(builder);
continue_block_id = vkd3d_spirv_alloc_id(builder);
merge_block_id = vkd3d_spirv_alloc_id(builder);
vkd3d_spirv_build_op_branch(builder, loop_header_block_id);
vkd3d_spirv_build_op_label(builder, loop_header_block_id);
vkd3d_spirv_build_op_loop_merge(builder, merge_block_id, continue_block_id, SpvLoopControlMaskNone);
vkd3d_spirv_build_op_branch(builder, loop_body_block_id);
vkd3d_spirv_build_op_label(builder, loop_body_block_id);
cf_info->u.loop.header_block_id = loop_header_block_id;
cf_info->u.loop.continue_block_id = continue_block_id;
cf_info->u.loop.merge_block_id = merge_block_id;
cf_info->current_block = VKD3D_BLOCK_LOOP;
vkd3d_spirv_build_op_name(builder, loop_header_block_id, "loop%u_header", compiler->loop_id);
vkd3d_spirv_build_op_name(builder, loop_body_block_id, "loop%u_body", compiler->loop_id);
vkd3d_spirv_build_op_name(builder, continue_block_id, "loop%u_continue", compiler->loop_id);
vkd3d_spirv_build_op_name(builder, merge_block_id, "loop%u_merge", compiler->loop_id);
++compiler->loop_id;
break;
case VKD3DSIH_ENDLOOP:
assert(compiler->control_flow_depth);
assert(cf_info->current_block == VKD3D_BLOCK_LOOP);
vkd3d_spirv_build_op_branch(builder, cf_info->u.loop.continue_block_id);
vkd3d_spirv_build_op_label(builder, cf_info->u.loop.continue_block_id);
vkd3d_spirv_build_op_branch(builder, cf_info->u.loop.header_block_id);
vkd3d_spirv_build_op_label(builder, cf_info->u.loop.merge_block_id);
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vkd3d_dxbc_compiler_pop_control_flow_level(compiler);
case VKD3DSIH_SWITCH:
if (!(cf_info = vkd3d_dxbc_compiler_push_control_flow_level(compiler)))
return;
merge_block_id = vkd3d_spirv_alloc_id(builder);
assert(src->reg.data_type == VKD3D_DATA_INT);
val_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src, VKD3DSP_WRITEMASK_0);
vkd3d_spirv_build_op_selection_merge(builder, merge_block_id, SpvSelectionControlMaskNone);
cf_info->u.switch_.id = compiler->switch_id;
cf_info->u.switch_.merge_block_id = merge_block_id;
cf_info->u.switch_.stream_location = vkd3d_spirv_stream_current_location(&builder->function_stream);
cf_info->u.switch_.selector_id = val_id;
cf_info->u.switch_.case_blocks = NULL;
cf_info->u.switch_.case_blocks_size = 0;
cf_info->u.switch_.case_block_count = 0;
vkd3d_array_reserve((void **)&cf_info->u.switch_.case_blocks, &cf_info->u.switch_.case_blocks_size,
10, sizeof(*cf_info->u.switch_.case_blocks));
cf_info->u.switch_.default_block_id = 0;
cf_info->inside_block = false;
cf_info->current_block = VKD3D_BLOCK_SWITCH;
vkd3d_spirv_build_op_name(builder, merge_block_id, "switch%u_merge", compiler->switch_id);
++compiler->switch_id;
break;
case VKD3DSIH_ENDSWITCH:
assert(compiler->control_flow_depth);
assert(cf_info->current_block == VKD3D_BLOCK_SWITCH);
assert(!cf_info->inside_block);
if (!cf_info->u.switch_.default_block_id)
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cf_info->u.switch_.default_block_id = cf_info->u.switch_.merge_block_id;
vkd3d_spirv_build_op_label(builder, cf_info->u.switch_.merge_block_id);
/* The OpSwitch instruction is inserted when the endswitch
* instruction is processed because we do not know the number
* of case statments in advance.*/
vkd3d_spirv_begin_function_stream_insertion(builder, cf_info->u.switch_.stream_location);
vkd3d_spirv_build_op_switch(builder, cf_info->u.switch_.selector_id,
cf_info->u.switch_.default_block_id, cf_info->u.switch_.case_blocks,
cf_info->u.switch_.case_block_count);
vkd3d_spirv_end_function_stream_insertion(builder);
vkd3d_free(cf_info->u.switch_.case_blocks);
vkd3d_dxbc_compiler_pop_control_flow_level(compiler);
break;
case VKD3DSIH_CASE:
{
uint32_t label_id, value;
assert(compiler->control_flow_depth);
assert(cf_info->current_block == VKD3D_BLOCK_SWITCH);
assert(src->swizzle == VKD3DSP_NOSWIZZLE && src->reg.type == VKD3DSPR_IMMCONST);
value = *src->reg.u.immconst_data;
if (!vkd3d_array_reserve((void **)&cf_info->u.switch_.case_blocks, &cf_info->u.switch_.case_blocks_size,
2 * (cf_info->u.switch_.case_block_count + 1), sizeof(*cf_info->u.switch_.case_blocks)))
return;
label_id = vkd3d_spirv_alloc_id(builder);
if (cf_info->inside_block) /* fall-through */
vkd3d_spirv_build_op_branch(builder, label_id);
cf_info->u.switch_.case_blocks[2 * cf_info->u.switch_.case_block_count + 0] = value;
cf_info->u.switch_.case_blocks[2 * cf_info->u.switch_.case_block_count + 1] = label_id;
++cf_info->u.switch_.case_block_count;
vkd3d_spirv_build_op_label(builder, label_id);
cf_info->inside_block = true;
vkd3d_spirv_build_op_name(builder, label_id, "switch%u_case%u", cf_info->u.switch_.id, value);
break;
}
case VKD3DSIH_DEFAULT:
assert(compiler->control_flow_depth);
assert(cf_info->current_block == VKD3D_BLOCK_SWITCH);
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assert(!cf_info->u.switch_.default_block_id);
cf_info->u.switch_.default_block_id = vkd3d_spirv_alloc_id(builder);
if (cf_info->inside_block) /* fall-through */
vkd3d_spirv_build_op_branch(builder, cf_info->u.switch_.default_block_id);
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vkd3d_spirv_build_op_label(builder, cf_info->u.switch_.default_block_id);
vkd3d_spirv_build_op_name(builder, cf_info->u.switch_.default_block_id,
"switch%u_default", cf_info->u.switch_.id);
cf_info->inside_block = true;
break;
case VKD3DSIH_BREAK:
{
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struct vkd3d_control_flow_info *breakable_cf_info;
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if (!(breakable_cf_info = vkd3d_dxbc_compiler_find_innermost_breakable_cf_construct(compiler)))
{
FIXME("Unhandled break instruction.\n");
return;
}
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assert(compiler->control_flow_depth);
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if (breakable_cf_info->current_block == VKD3D_BLOCK_LOOP)
{
vkd3d_spirv_build_op_branch(builder, breakable_cf_info->u.loop.merge_block_id);
}
else if (breakable_cf_info->current_block == VKD3D_BLOCK_SWITCH)
{
assert(breakable_cf_info->inside_block);
vkd3d_spirv_build_op_branch(builder, breakable_cf_info->u.switch_.merge_block_id);
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}
cf_info->inside_block = false;
break;
}
case VKD3DSIH_BREAKP:
assert(compiler->control_flow_depth);
assert(cf_info->current_block == VKD3D_BLOCK_LOOP);
vkd3d_dxbc_compiler_emit_breakc(compiler, instruction, cf_info->u.loop.merge_block_id);
break;
case VKD3DSIH_RET:
vkd3d_dxbc_compiler_emit_return(compiler, instruction);
if (cf_info)
cf_info->inside_block = false;
break;
case VKD3DSIH_TEXKILL:
vkd3d_dxbc_compiler_emit_kill(compiler, instruction);
break;
default:
ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
break;
}
}
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struct vkd3d_shader_image
{
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uint32_t image_id;
uint32_t sampler_id;
uint32_t sampled_image_id;
enum vkd3d_component_type sampled_type;
uint32_t image_type_id;
const struct vkd3d_spirv_resource_type *resource_type_info;
unsigned int structure_stride;
bool raw;
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};
#define VKD3D_IMAGE_FLAG_NONE 0x0
#define VKD3D_IMAGE_FLAG_DEPTH 0x1
#define VKD3D_IMAGE_FLAG_NO_LOAD 0x2
static const struct vkd3d_symbol *vkd3d_dxbc_compiler_find_resource(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_register *resource_reg)
{
struct vkd3d_symbol resource_key;
struct rb_entry *entry;
vkd3d_symbol_make_resource(&resource_key, resource_reg);
entry = rb_get(&compiler->symbol_table, &resource_key);
assert(entry);
return RB_ENTRY_VALUE(entry, struct vkd3d_symbol, entry);
}
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static void vkd3d_dxbc_compiler_prepare_image(struct vkd3d_dxbc_compiler *compiler,
struct vkd3d_shader_image *image, const struct vkd3d_shader_register *resource_reg,
unsigned int flags)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_symbol *resource_symbol;
bool load, depth_comparison;
load = !(flags & VKD3D_IMAGE_FLAG_NO_LOAD);
depth_comparison = flags & VKD3D_IMAGE_FLAG_DEPTH;
resource_symbol = vkd3d_dxbc_compiler_find_resource(compiler, resource_reg);
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image->sampled_type = resource_symbol->info.resource.sampled_type;
image->image_type_id = resource_symbol->info.resource.type_id;
image->resource_type_info = resource_symbol->info.resource.resource_type_info;
image->structure_stride = resource_symbol->info.resource.structure_stride;
image->raw = resource_symbol->info.resource.raw;
image->id = resource_symbol->id;
image->image_id = load ? vkd3d_spirv_build_op_load(builder,
image->image_type_id, image->id, SpvMemoryAccessMaskNone) : 0;
image->image_type_id = vkd3d_dxbc_compiler_get_image_type_id(compiler,
resource_reg, image->resource_type_info, image->sampled_type,
image->structure_stride || image->raw, depth_comparison);
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image->sampler_id = 0;
image->sampled_image_id = 0;
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static void vkd3d_dxbc_compiler_prepare_sampled_image_for_sampler(struct vkd3d_dxbc_compiler *compiler,
struct vkd3d_shader_image *image, const struct vkd3d_shader_register *resource_reg,
uint32_t sampler_var_id, unsigned int flags)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
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uint32_t sampled_image_type_id;
vkd3d_dxbc_compiler_prepare_image(compiler, image, resource_reg, flags);
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image->sampler_id = vkd3d_spirv_build_op_load(builder,
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vkd3d_spirv_get_op_type_sampler(builder), sampler_var_id, SpvMemoryAccessMaskNone);
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sampled_image_type_id = vkd3d_spirv_get_op_type_sampled_image(builder, image->image_type_id);
image->sampled_image_id = vkd3d_spirv_build_op_sampled_image(builder,
sampled_image_type_id, image->image_id, image->sampler_id);
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static void vkd3d_dxbc_compiler_prepare_default_sampled_image(struct vkd3d_dxbc_compiler *compiler,
struct vkd3d_shader_image *image, const struct vkd3d_shader_register *resource_reg)
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vkd3d_dxbc_compiler_prepare_sampled_image_for_sampler(compiler, image, resource_reg,
vkd3d_dxbc_compiler_get_default_sampler_id(compiler), false);
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}
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static void vkd3d_dxbc_compiler_prepare_sampled_image(struct vkd3d_dxbc_compiler *compiler,
struct vkd3d_shader_image *image, const struct vkd3d_shader_register *resource_reg,
const struct vkd3d_shader_register *sampler_reg, bool depth_comparison)
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{
vkd3d_dxbc_compiler_prepare_sampled_image_for_sampler(compiler, image, resource_reg,
vkd3d_dxbc_compiler_get_register_id(compiler, sampler_reg), depth_comparison);
}
static void vkd3d_dxbc_compiler_emit_ld(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
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const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
uint32_t image_id, type_id, coordinate_id, val_id;
SpvImageOperandsMask operands_mask = 0;
unsigned int image_operand_count = 0;
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struct vkd3d_shader_image image;
uint32_t image_operands[2];
DWORD coordinate_mask;
if (vkd3d_shader_instruction_has_texel_offset(instruction))
FIXME("Texel offset not supported.\n");
/* OpImageFetch must be used with a sampled image. */
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vkd3d_dxbc_compiler_prepare_default_sampled_image(compiler, &image, &src[1].reg);
image_id = vkd3d_spirv_build_op_image(builder, image.image_type_id, image.sampled_image_id);
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type_id = vkd3d_spirv_get_type_id(builder, image.sampled_type, VKD3D_VEC4_SIZE);
coordinate_mask = (1u << image.resource_type_info->coordinate_component_count) - 1;
coordinate_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], coordinate_mask);
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if (image.resource_type_info->resource_type != VKD3D_SHADER_RESOURCE_BUFFER)
{
operands_mask |= SpvImageOperandsLodMask;
image_operands[image_operand_count++] = vkd3d_dxbc_compiler_emit_load_src(compiler,
&src[0], VKD3DSP_WRITEMASK_3);
}
val_id = vkd3d_spirv_build_op_image_fetch(builder, type_id,
image_id, coordinate_id, operands_mask, image_operands, image_operand_count);
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vkd3d_dxbc_compiler_emit_store_dst_swizzled(compiler,
dst, val_id, image.sampled_type, src[1].swizzle);
static void vkd3d_dxbc_compiler_emit_sample(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
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const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
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uint32_t sampled_type_id, coordinate_id, val_id;
SpvImageOperandsMask operands_mask = 0;
unsigned int image_operand_count = 0;
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struct vkd3d_shader_image image;
uint32_t image_operands[1];
SpvOp op;
switch (instruction->handler_idx)
{
case VKD3DSIH_SAMPLE:
op = SpvOpImageSampleImplicitLod;
break;
case VKD3DSIH_SAMPLE_LOD:
op = SpvOpImageSampleExplicitLod;
operands_mask |= SpvImageOperandsLodMask;
image_operands[image_operand_count++] = vkd3d_dxbc_compiler_emit_load_src(compiler,
&src[3], VKD3DSP_WRITEMASK_0);
break;
default:
ERR("Unexpected instruction %#x.\n", instruction->handler_idx);
return;
}
if (vkd3d_shader_instruction_has_texel_offset(instruction))
FIXME("Texel offset not supported.\n");
vkd3d_dxbc_compiler_prepare_sampled_image(compiler, &image,
&src[1].reg, &src[2].reg, VKD3D_IMAGE_FLAG_NONE);
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sampled_type_id = vkd3d_spirv_get_type_id(builder, image.sampled_type, VKD3D_VEC4_SIZE);
coordinate_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], VKD3DSP_WRITEMASK_ALL);
val_id = vkd3d_spirv_build_op_image_sample(builder, op, sampled_type_id,
image.sampled_image_id, coordinate_id, operands_mask, image_operands, image_operand_count);
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vkd3d_dxbc_compiler_emit_store_dst_swizzled(compiler,
dst, val_id, image.sampled_type, src[1].swizzle);
static void vkd3d_dxbc_compiler_emit_sample_c(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
uint32_t sampled_type_id, coordinate_id, ref_id, val_id, type_id;
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
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const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
SpvImageOperandsMask operands_mask = 0;
unsigned int image_operand_count = 0;
struct vkd3d_shader_image image;
uint32_t image_operands[1];
SpvOp op;
if (vkd3d_shader_instruction_has_texel_offset(instruction))
FIXME("Texel offset not supported.\n");
if (instruction->handler_idx == VKD3DSIH_SAMPLE_C_LZ)
{
op = SpvOpImageSampleDrefExplicitLod;
operands_mask |= SpvImageOperandsLodMask;
image_operands[image_operand_count++]
= vkd3d_dxbc_compiler_get_constant_float(compiler, 0.0f);
}
else
{
op = SpvOpImageSampleDrefImplicitLod;
}
vkd3d_dxbc_compiler_prepare_sampled_image(compiler,
&image, &src[1].reg, &src[2].reg, VKD3D_IMAGE_FLAG_DEPTH);
sampled_type_id = vkd3d_spirv_get_type_id(builder, image.sampled_type, 1);
coordinate_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], VKD3DSP_WRITEMASK_ALL);
ref_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[3], VKD3DSP_WRITEMASK_0);
/* XXX: Nvidia is broken and expects that the D_ref is packed together with coordinates. */
type_id = vkd3d_spirv_get_type_id(builder, VKD3D_TYPE_FLOAT, VKD3D_VEC4_SIZE);
coordinate_id = vkd3d_spirv_build_op_composite_insert(builder,
type_id, ref_id, coordinate_id, &image.resource_type_info->coordinate_component_count, 1);
val_id = vkd3d_spirv_build_op_image_sample_dref(builder, op, sampled_type_id,
image.sampled_image_id, coordinate_id, ref_id, operands_mask,
image_operands, image_operand_count);
vkd3d_dxbc_compiler_emit_store_dst_scalar(compiler,
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dst, val_id, image.sampled_type, src[1].swizzle);
static uint32_t vkd3d_dxbc_compiler_emit_texel_offset(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction,
const struct vkd3d_spirv_resource_type *resource_type_info)
{
const struct vkd3d_shader_texel_offset *offset = &instruction->texel_offset;
unsigned int component_count = resource_type_info->offset_component_count;
int32_t data[4] = {offset->u, offset->v, offset->w, 0};
return vkd3d_dxbc_compiler_get_constant(compiler,
VKD3D_TYPE_INT, component_count, (const uint32_t *)data);
}
static void vkd3d_dxbc_compiler_emit_gather4(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
uint32_t sampled_type_id, coordinate_id, component_id, val_id;
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committed
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
const struct vkd3d_shader_src_param *resource, *sampler;
SpvImageOperandsMask operands_mask = 0;
unsigned int image_operand_count = 0;
struct vkd3d_shader_image image;
unsigned int component_idx;
uint32_t image_operands[1];
DWORD coordinate_mask;
resource = &src[1];
sampler = &src[2];
component_idx = vkd3d_swizzle_get_component(sampler->swizzle, 0);
/* Nvidia driver requires signed integer type. */
component_id = vkd3d_dxbc_compiler_get_constant(compiler, VKD3D_TYPE_INT, 1, &component_idx);
vkd3d_dxbc_compiler_prepare_sampled_image(compiler, &image,
&resource->reg, &sampler->reg, VKD3D_IMAGE_FLAG_NONE);
if (vkd3d_shader_instruction_has_texel_offset(instruction))
{
operands_mask |= SpvImageOperandsConstOffsetMask;
image_operands[image_operand_count++] = vkd3d_dxbc_compiler_emit_texel_offset(compiler,
instruction, image.resource_type_info);
}
sampled_type_id = vkd3d_spirv_get_type_id(builder, image.sampled_type, VKD3D_VEC4_SIZE);
coordinate_mask = (1u << image.resource_type_info->coordinate_component_count) - 1;
coordinate_id = vkd3d_dxbc_compiler_emit_load_src(compiler, &src[0], coordinate_mask);
val_id = vkd3d_spirv_build_op_image_gather(builder, sampled_type_id,
image.sampled_image_id, coordinate_id, component_id,
operands_mask, image_operands, image_operand_count);
Józef Kucia
committed
vkd3d_dxbc_compiler_emit_store_dst_swizzled(compiler,
dst, val_id, image.sampled_type, resource->swizzle);
static uint32_t vkd3d_dxbc_compiler_emit_raw_structured_addressing(
struct vkd3d_dxbc_compiler *compiler, uint32_t type_id, unsigned int stride,
const struct vkd3d_shader_src_param *src0, DWORD src0_mask,
const struct vkd3d_shader_src_param *src1, DWORD src1_mask)
{
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_src_param *offset;
uint32_t structure_id = 0, offset_id;
DWORD offset_write_mask;
if (stride)
structure_id = vkd3d_dxbc_compiler_emit_load_src(compiler, src0, src0_mask);
structure_id = vkd3d_spirv_build_op_imul(builder, type_id,
structure_id, vkd3d_dxbc_compiler_get_constant_uint(compiler, stride));
}
offset = stride ? src1 : src0;
offset_write_mask = stride ? src1_mask : src0_mask;
offset_id = vkd3d_dxbc_compiler_emit_load_src(compiler, offset, offset_write_mask);
offset_id = vkd3d_spirv_build_op_shift_right_logical(builder, type_id,
offset_id, vkd3d_dxbc_compiler_get_constant_uint(compiler, 2));
if (structure_id)
return vkd3d_spirv_build_op_iadd(builder, type_id, structure_id, offset_id);
else
return offset_id;
}
static void vkd3d_dxbc_compiler_emit_ld_raw_structured_srv_uav(struct vkd3d_dxbc_compiler *compiler,
const struct vkd3d_shader_instruction *instruction)
{
uint32_t coordinate_id, type_id, val_id, image_id, texel_type_id;
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
const struct vkd3d_shader_dst_param *dst = instruction->dst;
const struct vkd3d_shader_src_param *src = instruction->src;
const struct vkd3d_shader_src_param *resource;
uint32_t base_coordinate_id, component_idx;
uint32_t constituents[VKD3D_VEC4_SIZE];
struct vkd3d_shader_image image;
resource = &src[instruction->src_count - 1];
if (resource->reg.type == VKD3DSPR_RESOURCE)
{
/* OpImageFetch must be used with a sampled image. */
op = SpvOpImageFetch;