- Dec 18, 2024
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Francisco Casas authored
For SM1 the lod bias should be in src0.w.
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navi authored
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- Dec 17, 2024
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Henri Verbeet authored
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- Dec 12, 2024
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Giovanni Mascellani authored
The previous names "not normalised" and "fully normalised" have meanings which are likely to change with time. OTOH including a description of the normalisation level in the enumerant seems excessive. Relating normalisation levels to shader model versions might be a reasonable compromise.
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Elizabeth Figura authored
The previous format matched sm1 and sm4, but if we're going to be feeding everything through vsir, we want vsir's format.
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Elizabeth Figura authored
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Elizabeth Figura authored
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Victor Chiletto authored
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Victor Chiletto authored
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Victor Chiletto authored
We need 'for' iter blocks to be separate for loop unrolling.
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Victor Chiletto authored
Since loop unrolling doesn't clone the entire program anymore, we can express it as a hlsl_transform_ir() transform.
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Victor Chiletto authored
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Victor Chiletto authored
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Victor Chiletto authored
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Victor Chiletto authored
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- Dec 11, 2024
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Shaun Ren authored
We normalize binary expressions by attempting to group constants together, in order to facilitate further simplification of the expressions. For any binary operator OP, non-constants x, y, and constants a, b, we apply the following rewrite rules: a OP x -> x OP a, if OP is commutative. (x OP a) OP b -> x OP (a OP b), if OP is associative. (x OP a) OP y -> (x OP y) OP a, if OP is associative and commutative. x OP (y OP a) -> (x OP y) OP a, if OP is associative. Note that we consider floating point operations to be non-associative.
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- Dec 10, 2024
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Francisco Casas authored
This completes the hlsl->vsir->tpf translation.
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Francisco Casas authored
The alternative to adding the vsir_program->tess_output_primitive and vsir_program->tess_partitioning fields would be to emit the vsir DCL_TESSELLATOR_OUTPUT_PRIMITIVE and DCL_TESSELLATOR_PARTITIONING instructions, like DXIL does, but I think that the preference is to store these kind of data directly in the vsir_program.
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Francisco Casas authored
For consistency with the sm4_generate_rdef() and sm4_generate_vsir() functions.
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
The combined sampler is created as a SAMPLER instead of a TEXTURE because that fits all our current infrastructure. The only problem is that in the CTAB it must appear as a Texture, so the new field hlsl_type.is_combined_sampler is added. Co-authored-by:
Elizabeth Figura <zfigura@codeweavers.com>
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- Dec 09, 2024
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Francisco Casas authored
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Francisco Casas authored
Looking at the implementation of shader_sm4_read_dcl_sampler(), vsir stores the resource index range both in vkd3d_shader_instruction.declaration.sampler.range and in the vkd3d_shader_instruction.declaration.sampler.src.reg.idx[1-2] indexes, so we do the same. It is also worth noting that for shader models lower than 5.1, vsir has a normalization on the ins->declaration src register indexes. Refer to the following comment: /* SM5.1 places a symbol identifier in idx[0] and moves * other values up one slot. Normalize to SM5.1. */ on shader_sm4_read_param(). This normalization is also added to the generated vsir instructions.
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Francisco Casas authored
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Francisco Casas authored
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- Nov 27, 2024
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Francisco Casas authored
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Francisco Casas authored
Translate the instructions that contain hlsl_blocks. Also move other control flow instructions such as HS_CONTROL_POINT_PHASE and RET to the vsir_program so that we can directly iterate over it now.
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Francisco Casas authored
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- Nov 23, 2024
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
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Francisco Casas authored
These system values are bound to the same allocation rules as other semantics: they can share registers with other semantics with the same interpolation mode and they prefer forming shorter writemasks. However, for some reason, these don't allow further semantics to share the same register once allocated, except among themselves.
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- Nov 21, 2024
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navi authored
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