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token = (1u << 31);
token |= res_type << VKD3D_SM1_RESOURCE_TYPE_SHIFT;
put_u32(buffer, token);
reg.type = D3DSPR_SAMPLER;
reg.writemask = VKD3DSP_WRITEMASK_ALL;
reg.reg = reg_id;
write_sm1_dst_register(buffer, ®);
}
static void write_sm1_sampler_dcls(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer)
{
enum hlsl_sampler_dim sampler_dim;
unsigned int i, count, reg_id;
struct hlsl_ir_var *var;
if (ctx->profile->major_version < 2)
return;
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
{
if (!var->regs[HLSL_REGSET_SAMPLERS].allocated)
continue;

Francisco Casas
committed
count = var->bind_count[HLSL_REGSET_SAMPLERS];
for (i = 0; i < count; ++i)
{
if (var->objects_usage[HLSL_REGSET_SAMPLERS][i].used)
{
sampler_dim = var->objects_usage[HLSL_REGSET_SAMPLERS][i].sampler_dim;
if (sampler_dim == HLSL_SAMPLER_DIM_GENERIC)
{
/* These can appear in sm4-style combined sample instructions. */
hlsl_fixme(ctx, &var->loc, "Generic samplers need to be lowered.");
continue;
}
reg_id = var->regs[HLSL_REGSET_SAMPLERS].id + i;
write_sm1_sampler_dcl(ctx, buffer, reg_id, sampler_dim);
}
}
}
}
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static void write_sm1_constant(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer,
const struct hlsl_ir_node *instr)
{
const struct hlsl_ir_constant *constant = hlsl_ir_constant(instr);
struct sm1_instruction sm1_instr =
{
.opcode = D3DSIO_MOV,
.dst.type = D3DSPR_TEMP,
.dst.reg = instr->reg.id,
.dst.writemask = instr->reg.writemask,
.has_dst = 1,
.srcs[0].type = D3DSPR_CONST,
.srcs[0].reg = constant->reg.id,
.srcs[0].swizzle = hlsl_swizzle_from_writemask(constant->reg.writemask),
.src_count = 1,
};
assert(instr->reg.allocated);
assert(constant->reg.allocated);
sm1_map_src_swizzle(&sm1_instr.srcs[0], sm1_instr.dst.writemask);
write_sm1_instruction(ctx, buffer, &sm1_instr);
}
static void write_sm1_per_component_unary_op(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer,
const struct hlsl_ir_node *instr, D3DSHADER_INSTRUCTION_OPCODE_TYPE opcode)
{
struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
struct hlsl_ir_node *arg1 = expr->operands[0].node;
unsigned int i;
for (i = 0; i < instr->data_type->dimx; ++i)
{
struct hlsl_reg src = arg1->reg, dst = instr->reg;
src.writemask = hlsl_combine_writemasks(src.writemask, 1u << i);
dst.writemask = hlsl_combine_writemasks(dst.writemask, 1u << i);
write_sm1_unary_op(ctx, buffer, opcode, &dst, &src, 0, 0);
}
}
static void write_sm1_expr(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
{
struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
struct hlsl_ir_node *arg1 = expr->operands[0].node;
struct hlsl_ir_node *arg2 = expr->operands[1].node;
struct hlsl_ir_node *arg3 = expr->operands[2].node;
assert(instr->reg.allocated);
if (instr->data_type->base_type != HLSL_TYPE_FLOAT)
{
/* These need to be lowered. */
hlsl_fixme(ctx, &instr->loc, "SM1 non-float expression.");
return;
}
switch (expr->op)
{
case HLSL_OP1_ABS:
write_sm1_unary_op(ctx, buffer, D3DSIO_ABS, &instr->reg, &arg1->reg, 0, 0);
break;
case HLSL_OP1_DSX:
write_sm1_unary_op(ctx, buffer, D3DSIO_DSX, &instr->reg, &arg1->reg, 0, 0);
break;
case HLSL_OP1_DSY:
write_sm1_unary_op(ctx, buffer, D3DSIO_DSY, &instr->reg, &arg1->reg, 0, 0);
break;
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case HLSL_OP1_EXP2:
write_sm1_per_component_unary_op(ctx, buffer, instr, D3DSIO_EXP);
break;
case HLSL_OP1_LOG2:
write_sm1_per_component_unary_op(ctx, buffer, instr, D3DSIO_LOG);
break;
case HLSL_OP1_NEG:
write_sm1_unary_op(ctx, buffer, D3DSIO_MOV, &instr->reg, &arg1->reg, D3DSPSM_NEG, 0);
break;
case HLSL_OP1_SAT:
write_sm1_unary_op(ctx, buffer, D3DSIO_MOV, &instr->reg, &arg1->reg, 0, D3DSPDM_SATURATE);
break;
case HLSL_OP1_RCP:
write_sm1_per_component_unary_op(ctx, buffer, instr, D3DSIO_RCP);
break;
case HLSL_OP1_RSQ:
write_sm1_per_component_unary_op(ctx, buffer, instr, D3DSIO_RSQ);
break;
case HLSL_OP2_ADD:
write_sm1_binary_op(ctx, buffer, D3DSIO_ADD, &instr->reg, &arg1->reg, &arg2->reg);
break;
case HLSL_OP2_MAX:
write_sm1_binary_op(ctx, buffer, D3DSIO_MAX, &instr->reg, &arg1->reg, &arg2->reg);
break;
case HLSL_OP2_MIN:
write_sm1_binary_op(ctx, buffer, D3DSIO_MIN, &instr->reg, &arg1->reg, &arg2->reg);
break;
case HLSL_OP2_MUL:
write_sm1_binary_op(ctx, buffer, D3DSIO_MUL, &instr->reg, &arg1->reg, &arg2->reg);
break;
case HLSL_OP1_FRACT:
write_sm1_unary_op(ctx, buffer, D3DSIO_FRC, &instr->reg, &arg1->reg, D3DSPSM_NONE, 0);
break;
case HLSL_OP2_DOT:
switch (arg1->data_type->dimx)
{
case 4:
write_sm1_binary_op_dot(ctx, buffer, D3DSIO_DP4, &instr->reg, &arg1->reg, &arg2->reg);
break;
case 3:
write_sm1_binary_op_dot(ctx, buffer, D3DSIO_DP3, &instr->reg, &arg1->reg, &arg2->reg);
break;
default:
vkd3d_unreachable();
}
break;
case HLSL_OP3_DP2ADD:
write_sm1_dp2add(ctx, buffer, &instr->reg, &arg1->reg, &arg2->reg, &arg3->reg);
break;
default:
hlsl_fixme(ctx, &instr->loc, "SM1 \"%s\" expression.", debug_hlsl_expr_op(expr->op));
break;
}
}
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static void write_sm1_jump(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
{
const struct hlsl_ir_jump *jump = hlsl_ir_jump(instr);
switch (jump->type)
{
case HLSL_IR_JUMP_DISCARD_NEG:
{
struct hlsl_reg *reg = &jump->condition.node->reg;
struct sm1_instruction instr =
{
.opcode = VKD3D_SM1_OP_TEXKILL,
.dst.type = D3DSPR_TEMP,
.dst.reg = reg->id,
.dst.writemask = reg->writemask,
.has_dst = 1,
};
write_sm1_instruction(ctx, buffer, &instr);
break;
}
default:
hlsl_fixme(ctx, &jump->node.loc, "Jump type %s.\n", hlsl_jump_type_to_string(jump->type));
}
}
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static void write_sm1_load(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
{
const struct hlsl_ir_load *load = hlsl_ir_load(instr);
const struct hlsl_reg reg = hlsl_reg_from_deref(ctx, &load->src);
struct sm1_instruction sm1_instr =
{
.opcode = D3DSIO_MOV,
.dst.type = D3DSPR_TEMP,
.dst.reg = instr->reg.id,
.dst.writemask = instr->reg.writemask,
.has_dst = 1,
.srcs[0].type = D3DSPR_TEMP,
.srcs[0].reg = reg.id,
.srcs[0].swizzle = hlsl_swizzle_from_writemask(reg.writemask),
.src_count = 1,
};
assert(instr->reg.allocated);
if (load->src.var->is_uniform)
{
assert(reg.allocated);
sm1_instr.srcs[0].type = D3DSPR_CONST;
}
else if (load->src.var->is_input_semantic)
{
if (!hlsl_sm1_register_from_semantic(ctx, &load->src.var->semantic,
false, &sm1_instr.srcs[0].type, &sm1_instr.srcs[0].reg))
{
assert(reg.allocated);
sm1_instr.srcs[0].type = D3DSPR_INPUT;
sm1_instr.srcs[0].reg = reg.id;
}
else
sm1_instr.srcs[0].swizzle = hlsl_swizzle_from_writemask((1 << load->src.var->data_type->dimx) - 1);
}
sm1_map_src_swizzle(&sm1_instr.srcs[0], sm1_instr.dst.writemask);
write_sm1_instruction(ctx, buffer, &sm1_instr);
}
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static void write_sm1_resource_load(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer,
const struct hlsl_ir_node *instr)
{
const struct hlsl_ir_resource_load *load = hlsl_ir_resource_load(instr);
struct hlsl_ir_node *coords = load->coords.node;
unsigned int sampler_offset, reg_id;
struct sm1_instruction sm1_instr;
sampler_offset = hlsl_offset_from_deref_safe(ctx, &load->resource);
reg_id = load->resource.var->regs[HLSL_REGSET_SAMPLERS].id + sampler_offset;
sm1_instr = (struct sm1_instruction)
{
.opcode = D3DSIO_TEX,
.dst.type = D3DSPR_TEMP,
.dst.reg = instr->reg.id,
.dst.writemask = instr->reg.writemask,
.has_dst = 1,
.srcs[0].type = D3DSPR_TEMP,
.srcs[0].reg = coords->reg.id,
.srcs[0].swizzle = hlsl_swizzle_from_writemask(VKD3DSP_WRITEMASK_ALL),
.srcs[1].type = D3DSPR_SAMPLER,
.srcs[1].reg = reg_id,
.srcs[1].swizzle = hlsl_swizzle_from_writemask(VKD3DSP_WRITEMASK_ALL),
.src_count = 2,
};
assert(instr->reg.allocated);
write_sm1_instruction(ctx, buffer, &sm1_instr);
}
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static void write_sm1_store(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer,
const struct hlsl_ir_node *instr)
{
const struct hlsl_ir_store *store = hlsl_ir_store(instr);
const struct hlsl_ir_node *rhs = store->rhs.node;
const struct hlsl_reg reg = hlsl_reg_from_deref(ctx, &store->lhs);
struct sm1_instruction sm1_instr =
{
.opcode = D3DSIO_MOV,
.dst.type = D3DSPR_TEMP,
.dst.reg = reg.id,
.dst.writemask = hlsl_combine_writemasks(reg.writemask, store->writemask),
.has_dst = 1,
.srcs[0].type = D3DSPR_TEMP,
.srcs[0].reg = rhs->reg.id,
.srcs[0].swizzle = hlsl_swizzle_from_writemask(rhs->reg.writemask),
.src_count = 1,
};
if (store->lhs.var->data_type->class == HLSL_CLASS_MATRIX)
{
FIXME("Matrix writemasks need to be lowered.\n");
return;
}
if (store->lhs.var->is_output_semantic)
{
if (ctx->profile->type == VKD3D_SHADER_TYPE_PIXEL && ctx->profile->major_version == 1)
{
sm1_instr.dst.type = D3DSPR_TEMP;
sm1_instr.dst.reg = 0;
}
else if (!hlsl_sm1_register_from_semantic(ctx, &store->lhs.var->semantic,
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true, &sm1_instr.dst.type, &sm1_instr.dst.reg))
{
assert(reg.allocated);
sm1_instr.dst.type = D3DSPR_OUTPUT;
sm1_instr.dst.reg = reg.id;
}
else
sm1_instr.dst.writemask = (1u << store->lhs.var->data_type->dimx) - 1;
}
else
assert(reg.allocated);
sm1_map_src_swizzle(&sm1_instr.srcs[0], sm1_instr.dst.writemask);
write_sm1_instruction(ctx, buffer, &sm1_instr);
}
static void write_sm1_swizzle(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer,
const struct hlsl_ir_node *instr)
{
const struct hlsl_ir_swizzle *swizzle = hlsl_ir_swizzle(instr);
const struct hlsl_ir_node *val = swizzle->val.node;
struct sm1_instruction sm1_instr =
{
.opcode = D3DSIO_MOV,
.dst.type = D3DSPR_TEMP,
.dst.reg = instr->reg.id,
.dst.writemask = instr->reg.writemask,
.has_dst = 1,
.srcs[0].type = D3DSPR_TEMP,
.srcs[0].reg = val->reg.id,
.srcs[0].swizzle = hlsl_combine_swizzles(hlsl_swizzle_from_writemask(val->reg.writemask),
swizzle->swizzle, instr->data_type->dimx),
.src_count = 1,
};
assert(instr->reg.allocated);
assert(val->reg.allocated);
sm1_map_src_swizzle(&sm1_instr.srcs[0], sm1_instr.dst.writemask);
write_sm1_instruction(ctx, buffer, &sm1_instr);
}
static void write_sm1_instructions(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffer *buffer,
const struct hlsl_ir_function_decl *entry_func)
{
const struct hlsl_ir_node *instr;
LIST_FOR_EACH_ENTRY(instr, &entry_func->body.instrs, struct hlsl_ir_node, entry)
{
if (instr->data_type)
{
if (instr->data_type->class == HLSL_CLASS_MATRIX)
{
/* These need to be lowered. */
hlsl_fixme(ctx, &instr->loc, "SM1 matrix expression.");
continue;
}
else if (instr->data_type->class == HLSL_CLASS_OBJECT)
{
hlsl_fixme(ctx, &instr->loc, "Object copy.");
break;
}
assert(instr->data_type->class == HLSL_CLASS_SCALAR || instr->data_type->class == HLSL_CLASS_VECTOR);
}
switch (instr->type)
{
case HLSL_IR_CALL:
vkd3d_unreachable();
case HLSL_IR_CONSTANT:
write_sm1_constant(ctx, buffer, instr);
break;
case HLSL_IR_EXPR:
write_sm1_expr(ctx, buffer, instr);
break;
case HLSL_IR_JUMP:
write_sm1_jump(ctx, buffer, instr);
break;
case HLSL_IR_LOAD:
write_sm1_load(ctx, buffer, instr);
break;
case HLSL_IR_RESOURCE_LOAD:
write_sm1_resource_load(ctx, buffer, instr);
break;
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case HLSL_IR_STORE:
write_sm1_store(ctx, buffer, instr);
break;
case HLSL_IR_SWIZZLE:
write_sm1_swizzle(ctx, buffer, instr);
break;
default:
hlsl_fixme(ctx, &instr->loc, "Instruction type %s.", hlsl_node_type_to_string(instr->type));
}
}
}
int hlsl_sm1_write(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl *entry_func, struct vkd3d_shader_code *out)
{
struct vkd3d_bytecode_buffer buffer = {0};
put_u32(&buffer, sm1_version(ctx->profile->type, ctx->profile->major_version, ctx->profile->minor_version));
write_sm1_uniforms(ctx, &buffer, entry_func);
write_sm1_constant_defs(ctx, &buffer);
write_sm1_semantic_dcls(ctx, &buffer);
write_sm1_sampler_dcls(ctx, &buffer);
write_sm1_instructions(ctx, &buffer, entry_func);
put_u32(&buffer, D3DSIO_END);
if (buffer.status)
ctx->result = buffer.status;
if (!ctx->result)
{
out->code = buffer.data;
out->size = buffer.size;
}
else
{
vkd3d_free(buffer.data);
}
return ctx->result;