Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
wine
Manage
Activity
Members
Labels
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Package registry
Container registry
Model registry
Operate
Terraform modules
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Lorenzo Ferrillo
wine
Commits
ad1d7450
Commit
ad1d7450
authored
13 years ago
by
André Zwing
Committed by
Alexandre Julliard
13 years ago
Browse files
Options
Downloads
Patches
Plain Diff
winedbg: Fix parsing table for ARM disassembler.
parent
b8d07a2b
Branches
Branches containing commit
Tags
Tags containing commit
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
programs/winedbg/be_arm.c
+12
-2
12 additions, 2 deletions
programs/winedbg/be_arm.c
with
12 additions
and
2 deletions
programs/winedbg/be_arm.c
+
12
−
2
View file @
ad1d7450
...
...
@@ -102,12 +102,19 @@ static UINT arm_disasm_branch(UINT inst)
return
0
;
}
static
UINT
arm_disasm_branchreg
(
UINT
inst
)
{
dbg_printf
(
"
\n\t
b%s
\t
%s"
,
get_cond
(
inst
),
tbl_regs
[
get_nibble
(
inst
,
0
)]);
return
0
;
}
static
UINT
arm_disasm_dataprocessing
(
UINT
inst
)
{
short
condcodes
=
(
inst
>>
20
)
&
0x01
;
short
opcode
=
(
inst
>>
21
)
&
0x0f
;
short
immediate
=
(
inst
>>
25
)
&
0x01
;
short
no_op1
=
(
opcode
&
0x0d
)
==
0x0d
;
short
no_dst
=
(
opcode
&
0x0c
)
==
0x08
;
/* check for nop */
if
(
get_nibble
(
inst
,
3
)
==
15
/* r15 */
&&
condcodes
==
0
&&
...
...
@@ -118,7 +125,9 @@ static UINT arm_disasm_dataprocessing(UINT inst)
}
dbg_printf
(
"
\n\t
%s%s%s"
,
tbl_dataops
[
opcode
],
condcodes
?
"s"
:
""
,
get_cond
(
inst
));
dbg_printf
(
"
\t
%s, "
,
tbl_regs
[
get_nibble
(
inst
,
3
)]);
if
(
!
no_dst
)
dbg_printf
(
"
\t
%s, "
,
tbl_regs
[
get_nibble
(
inst
,
3
)]);
else
dbg_printf
(
"
\t
"
);
if
(
no_op1
)
{
if
(
immediate
)
...
...
@@ -395,9 +404,10 @@ struct inst_arm
static
const
struct
inst_arm
tbl_arm
[]
=
{
{
0x0e000000
,
0x0a000000
,
arm_disasm_branch
},
{
0x0e000090
,
0x00000090
,
arm_disasm_halfwordtrans
},
{
0x0fffff00
,
0x012fff00
,
arm_disasm_branchreg
},
{
0x0c000000
,
0x00000000
,
arm_disasm_dataprocessing
},
{
0x0c000000
,
0x04000000
,
arm_disasm_singletrans
},
{
0x0e000090
,
0x00000090
,
arm_disasm_halfwordtrans
},
{
0x0e000000
,
0x08000000
,
arm_disasm_blocktrans
},
{
0x0f000000
,
0x0f000000
,
arm_disasm_swi
},
{
0x0f000010
,
0x0e000010
,
arm_disasm_coproctrans
},
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment